The prototype known as TRIPS -- Tera-op, Reliable, Intelligently adaptive Processing System -- was designed and built by a team of computer scientists at the University of Texas at Austin.

Professors Stephen Keckler, Doug Burger, Kathryn McKinley and their colleagues spent seven years creating the underlying technology that culminated in the chip.

Burger said TRIPS uses a new class of processing architectures called Explicit Data Graph Execution, or EDGE. Unlike conventional computer architectures that process one instruction at a time, EDGE processes large blocks of information simultaneously.

A TRIPS chip contains two processing cores, each of which can issue 16 operations per cycle with up to 1,024 instructions in flight simultaneously. Current high-performance processors are typically designed to sustain a maximum execution rate of four operations per cycle.

The researchers will unveil a fully functional TRIPS prototype during a public presentation Monday at The University of Texas at Austin. Additional information is available online at oea.cs.utexas.edu/articles/index2007/trips_unveiling07.html.